The present invention relates generally to integrated circuits, and more specifically to synchronizing an external clock signal applied to an integrated circuit with internal clock signals generated in the integrated circuit in response to the external clock signal.
In synchronous integrated circuits, the integrated circuit is clocked by an external clock signal and performs operations at predetermined times relative the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memories (SDRAMs), synchronous static random access memories (SSRAMs), and packetized memories like SLDRAMs and RDRAMs, and include other types of integrated circuits as well, such as microprocessors. The timing of signals external to a synchronous memory device is determined by the external clock signal, and operations within the memory device typically must be synchronized to external operations. For example, commands are placed on a command bus of the memory device in synchronism with the external clock signal, and the memory device must latch these commands at the proper times to successfully capture the commands. To latch the applied commands, an internal clock signal is developed in response to the external clock signal, and is typically applied to latches contained in the memory device to thereby clock the commands into the latches. The internal clock signal and external clock must be synchronized to ensure the internal clock signal clocks the latches at the proper times to successfully capture the commands. In the present description, xe2x80x9cexternalxe2x80x9d is used to refer to signals and operations outside of the memory device, and xe2x80x9cinternalxe2x80x9d to refer to signals and operations within the memory device. Moreover, although the present description is directed to synchronous memory devices, the principles described herein are equally applicable to other types of synchronous integrated circuits.
Internal circuitry in the memory device that generates the internal clock signal necessarily introduces some time delay, causing the internal clock signal to be phase shifted relative to the external clock signal. As long as the phase-shift is minimal, timing within the memory device can be easily synchronized to the external timing. To increase the rate at which commands can be applied and at which data can be transferred to and from the memory device, the frequency of the external clock signal is increased, and in modern synchronous memories the frequency is in excess of 100 MHZ. As the frequency of the external clock signal increases, however, the time delay introduced by the internal circuitry becomes more significant. This is true because as the frequency of the external clock signal increases, the period of the signal decreases and thus even small delays introduced by the internal circuitry correspond to significant phase shifts between the internal and external clock signals. As a result, the commands applied to the memory device may no longer be valid by the time the internal clock signal clocks the latches.
To synchronize external and internal clock signals in modern synchronous memory devices, a number of different approaches have been considered and utilized, including delay-locked loops (DLLs), phased-locked loops (PLLs), and synchronous mirror delays (SMDs), as will be appreciated by those skilled in the art. As used herein, the term synchronized includes signals that are coincident and signals that have a desired delay relative to one another. FIG. 1 is a functional block diagram illustrating a conventional delay-locked loop 100 including a variable delay line 102 that receives a clock buffer signal CLKBUF and generates a delayed clock signal CLKDEL in response to the clock buffer signal. The variable delay line 102 controls a variable delay VD of the CLKDEL signal relative to the CLKBUF signal in response to a delay adjustment signal DADJ. A feedback delay line 104 generates a feedback clock signal CLKFB in response to the CLKDEL signal, the feedback clock signal having a model delay D1+D2 relative to the CLKDEL signal. The D1 component of the model delay D1+D2 corresponds to a delay introduced by an input buffer 106 that generates the CLKBUF signal in response to an external clock signal CLK, while the D2 component of the model delay corresponds to a delay introduced by an output buffer 108 that generates a synchronized clock signal CLKSYNC in response to the CLKDEL signal. Although the input buffer 106 and output buffer 108 are illustrated as single components, each represents all components and the associated delay between the input and output of the delay-locked loop 100. The input buffer 106 thus represents the delay D1 of all components between an input that receives the CLK signal and the input to the variable delay line 102, and the output buffer 108 represents the delay D2 of all components between the output of the variable delay line and an output at which the CLKSYNC signal is developed.
The delay-locked loop 100 further includes a phase detector 110 that receives the CLKFB and CLKBUF signals and generates a delay control signal DCONT having a value indicating the phase difference between the CLKBUF and CLKFB signals. One implementation of a phase detector is described in U.S. Pat. No. 5,946,244 to Manning (Manning), which is assigned to the assignee of the present patent application and which is incorporated herein by reference. A delay controller 112 generates the DADJ signal in response to the DCONT signal from the phase detector 110, and applies the DADJ signal to the variable delay line 102 to adjust the variable delay VD. The phase detector 110 and delay controller 112 operate in combination to adjust the variable delay VD of the variable delay line 102 as a function of the detected phase between the CLKBUF and CLKFB signals.
In operation, the phase detector 110 detects the phase difference between the CLKBUF and CLKFB signals, and the phase detector and delay controller 112 operate in combination to adjust the variable delay VD of the CLKDEL signal until the phase difference between the CLKBUF and CLKFB signals is approximately zero. More specifically, as the variable delay VD of the CLKDEL signal is adjusted the phase of the CLKFB signal from the feedback delay line 104 is adjusted accordingly until the CLKFB signal has approximately the same phase as the CLKBUF signal. When the delay-locked loop 100 has adjusted the variable delay VD to a value causing the phase shift between the CLKBUF and CLKFB signals to equal approximately zero, the delay-locked loop is said to be xe2x80x9clocked.xe2x80x9d When the delay-locked loop 100 is locked, the CLK and CLKSYNC signals are synchronized. This is true because when the phase shift between the CLKBUF and CLKFB signals is approximately zero (i.e., the delay-locked loop 100 is locked), the variable delay VD has a value of NTCKxe2x88x92(D1+D2) as indicated in FIG. 1, where N is an integer and TCK is the period of the CLK signal. When VD equals NTCKxe2x88x92(D1+D2), the total delay of the CLK signal through the input buffer 106, variable delay line 102, and output buffer 108 is D1+NTCKxe2x88x92(D1+D2)+D2, which equals NTCK. Thus, the CLKSYNC signal is delayed by NTCK relative to the CLK signal and the two signals are synchronized since the delay is an integer multiple of the period of the CLK signal. Referring back to the discussion of synchronous memory devices above, the CLK signal corresponds to the external clock signal and the CLKDEL signal corresponds to the internal clock signal.
FIG. 2 is a signal timing diagram illustrating various signals generated during operation of the delay-locked loop 100 of FIG. 1. In response to a rising-edge of the CLK signal at a time T0, the CLKBUF signal goes high the delay D1 later at a time T1. Initially, the variable delay VD as a value VD1, causing the CLKDEL signal to go high at a time T3 and the CLKSYNC signal to go high at a time T4. At this point, note that the positive-edge of the CLKSYNC signal at the time T4 is not synchronized with the CLK signal, which transitions high at a time T5. In response to the rising-edge of the CLKDEL signal at the time T3, the CLKFB goes high at a time T6, which occurs before a positive-edge of the CLKBUF signal occurring at a time T7. Thus, the positive-edge of the CLKFB signal occurs at the time T6 while the positive-edge of the CLKBUF occurs at the time T7, indicating there is a phase shift between the two signals. The phase detector 110 (FIG. 1) detects this phase difference, and generates the DCONT signal just after the time T7 at a time T8 which, in turn, causes the delay controller 112 (FIG. 1) to generate the DADJ signal to adjust the value of the variable delay VD to a new value VD2.
In response to the new variable delay VD2, the next rising-edge of the CLKDEL signal occurs at a time T9. The CLKSYNC signal transitions high the delay D2 later at a time T10 and in synchronism with a rising-edge of the CLK signal. At this point, the delay-locked loop 100 is locked. In response to the positive-edge transition of the CLKDEL signal at the time T9, the CLKFB signal transitions high at a time T11 in synchronism with the CLKBUF signal. Once again, the phase detector 110 (FIG. 1) detects the phase difference between the CLKBUF and CLKFB signals, which in this case, is approximately zero, and generates the DCONT signal just after the time T11 in response to the detected phase difference. In this situation, the generated DCONT signal would not cause the variable delay VD2 to be adjusted since the delay-locked loop 100 is locked. Moreover, although the relative, phases of the CLKBUF and CLKFB signals is detected in response to each rising-edge of these signals, the variable delay VD may not be adjusted immediately even where such a phase difference is detected. For example, the variable delay VD may be adjusted only when a phase difference between the CLKFB and CLKBUF signals exists for a predetermined time or exceeds a predetermined magnitude. In this way, the phase detector 110 and delay controller 112 can provide a sort of xe2x80x9cfilteringxe2x80x9d of jitter or variations in the CLK signal, as will be understood in the art.
In the delay-locked loop 100, each cycle of the CLK signal the phase detector 110 compares rising-edges of the CLKBUF and CLKFB signals and generates the appropriate DCONT signal to incrementally adjust the variable delay VD until the delay-locked loop 100 is locked. The phase detector 110 could also compare falling-edges of the CLKBUF and CLKFB signals, as in the previously mentioned Manning patent. In this way, the delay-locked loop 100 incrementally adjusts the variable delay VD once each cycle of the CLK signal. Although the example of FIG. 2 illustrates the delay-locked loop 100 as locking and therefore synchronizing the CLK and CLKSYNC signals after only two cycles of the CLK signal, the delay-locked loop typically takes as many as 200 cycles of the CLK signal to lock. Before the delay-locked loop 100 is locked, the CLKSYNC signal cannot be used to latch signals being applied to the synchronous memory device containing the delay-locked loop. As a result, the time it takes to lock the delay-locked loop 100 may slow the operation of the associated synchronous memory device. For example, in a conventional double data rate (DDR) SDRAM, the delay-locked loop is automatically disabled when the SDRAM enters a self-refresh mode of operation. Upon exiting the self-refresh mode, 200 cycles of the applied CLK signal must then occur before read or write data transfer commands can be applied to the SDRAM.
In the delay-locked loop 100, the variable delay line 102 is typically formed from a number of serially-connected individual delay stages, with individual delay stages being added or removed to adjust the variable delay VD, as will be understood by those skilled in the art. For example, a plurality of serially-connected inverters could be used to form the variable delay line 102, with the output from different inverters being selected in response to the DADJ to control the variable delay VD. A large number of stages in the variable delay line 102 is desirable with each stage having an incremental delay to provide better resolution in controlling the value of the variable delay VD, where the resolution of the delay-locked loop 100 is the smallest increment of delay that may be added and subtracted from the variable delay VD.
The variable delay line 102 may include separate coarse and fine delay lines that incrementally adjust the variable delay VD by a unit coarse delay CD and a unit fine delay FD, respectively, responsive to the DADJ signal. In this situation, the variable delay VD equals a number M of unit coarse delays CD being utilized plus a number N of unit fine delays FD being utilized (VD=Mxc3x97CD+Nxc3x97FD). By separating the delay line 102 into coarse and fine delay lines, the variable delay VD may be more quickly adjusted, enabling the delay-locked loop 100 to more quickly lock. With this approach, however, the resolution of the delay-locked loop 100 may be adversely affected by the use of separate coarse and fine delay lines due to the variations between the unit coarse delays CD and unit fine delays FD. Ideally, each unit coarse delay CD equals Q unit fine delays FD (CD=Qxc3x97FD) where Q is an integer. When Qxc3x97FD does not equal CD, the resolution of the delay-locked loop 100 may be adversely affected since the sum of the coarse delays CD plus the fine delays FD being utilized may vary from the desired variable delay VD by more than the fine delay FD, as will be appreciated by those skilled in the art.
In addition, the variable delay line 102 must be able to provide the maximum variable delay VD corresponding to the CLK signal having the lowest frequency in the frequency range over which the delay-locked loop is designed to operate. This is true because the variable delay line 102 must provide a variable delay VD of NTCKxe2x88x92(D1+D2), which will have its largest value when the period of the CLK signal is greatest, which occurs at the lowest frequency of the CLK signal. The desired fine resolution and maximum variable delay VD that the variable delay line 102 must provide can result in the delay line consisting of a large number of individual delay stages that consume a relatively large amount of space on a semiconductor substrate in which the delay-locked loop 100 and other components of the synchronous memory device are formed. Moreover, such a large number of individual delay stages can result in significant power consumption by the delay-locked loop 100, which may be undesirable particularly in applications where the synchronous memory device is contained in a portable battery-powered device.
There is a need for a delay-locked loop that occupies less space on a semiconductor substrate and consumes less power.
According to one aspect of the present invention a delay-locked loop includes a ring oscillator that generates a plurality of tap clock signals, with one tap clock signal being designated an oscillator clock signal. Each tap clock signal has a respective delay relative to the oscillator clock signal. A coarse delay circuit is coupled to the ring oscillator and generates a coarse delay count in response to the oscillator clock signal. The coarse delay circuit also generates a coarse reference count in response to a coarse delay control signal and activates a coarse delay enable signal in response to the coarse delay count being equal to the coarse delay reference count. The coarse delay circuit resets the coarse delay count responsive to a reset signal.
A fine delay circuit is coupled to the ring oscillator to receive the tap clock signals and operates in response to a fine delay control signal to select one of the tap clock signals that is then output as a fine delay enable signal. An output circuit is coupled to the coarse and fine delay circuits and generates a delayed clock signal responsive to the coarse and fine delay enable signals going active. The delayed clock signal is applied as the reset signal to the coarse delay circuit to reset the coarse delay count. A comparison circuit receives an input clock signal and is coupled to the output circuit to receive the delayed clock signal and also coupled to the coarse and fine delay circuits. The comparison circuit generates the coarse and fine delay control signals in response to the relative phases of the delayed and input clock signals.
According to another aspect of the present invention, the delay-locked loop monitors rising and falling edges of the input clock signal and develops corresponding rising-edge and falling-edge fine delays to synchronize rising and falling edges of the input clock signal. Dual coarse delays for rising and falling edges may also be timed.